A publication of the National Electronics Manufacturing Center of Excellence
December 2006
ACI EMPF

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American Competitiveness
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The EMPF is a U.S. Navy-sponsored National
Electronics Manufacturing Center of Excellence focused on the development, application, and transfer of new electronics manufacturing technology by partnering with industry, academia, and government centers and laboratories in the U.S

Technical Editor

Michael D. Frederickson,
EMPF Director

Please direct comments
and/or questions to the Editor at
empfasis-editor@aciusa.org
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In This Issue

Silicon-Germanium Flip Chip for RF Applications

 

Migration of Wirebonding to Flip-Chip

 

Ask the EMPF Helpline!

 

RF Modules Technology Roadmap

 

IPC 610 Electronic Assembly Acceptability

 

Tech Tips...S Parameter Testing for RF Applications

 

Manufacturer’s Corner: Seica Functional Test Equipment

 

Upcoming Training Center Courses


IAB
Industrial Advisory Board
Gerald R. Aschoff, The Boeing Company
Dennis M. Kox, Raytheon
Gregory X. Krieger, BAE Systems
Edward A. Morris, Lockheed Martin
Jack R. Harris, Rockwell Collins
Gary Kirchner, Honeywell
Andrew Paradise, Northrop Grumman
Art Smedberg, ITT Industries, Avionics Division


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title

 

Within the defense/aerospace sector, the re-hosting of legacy test programs from obsolete test equipment is critical to meet product sustainment requirements. As the life of Automatic Test Equipment (ATE) is often shorter than the life of the product or program, this condition may jeopardize usage of existing test environments and diminish through-life-support (TLS). In addition, the costs and time delays to migrate test program sets (TPS) to new ATE environments every few years, is not a cost-effective option.

Recently, a challenge was presented by a customer to migrate TPS from an obsolete test environment to the Seica Valid VIP Test System. The requirements posed by the end user were ambitious and demanded a comprehensive approach to the migration solution. The original ATE was equipped with 4 D2 (32 channels) and 10 D3 (240 channels) cards for digital test. The D3 channel cards were connected to corresponding A3 cards to become fully hybrid and assure analog test capabilities. The program did not take advantage of the multiplex capability of the ATE channel cards, so the effective requirement was limited to 272 hybrid pins/channels. The technology of the boards tested requires TTL levels; however, for some boards, digital, low speed signals between +-15V or 0/24V are required. All digital test programs were generated via LASAR simulation, but some local modification (or extensions, like memory tests) were apparent. Test programs were executed at moderate speed, usually around 2-3MHz, rarely reaching the 5MHz limit of the D3 channel cards. All digital test programs included go/no-go and guided probe diagnostics; the fault dictionary was not utilized.

Analog, parametric tests include DC force, and measure through I/O pins of the board, performed by internal ATE instrumentation routed via the A3 cards. Specific time/frequency tests were added using the internal time measurement system (TMS) and routing it through the digital 2-lines switching inherent with the structure of the digital channel cards.

For each TPS, validation of the migration process included, loop-testing against three boards and verification of the gooddiagnostic results via insertion of five physical faults.

The end user expressed the need to maintain the LASAR simulation environment to assure a comprehensive process of generation, validation, coverage assessment and easy modification for the digital part of the test programs. The Target Test System was an excellent match and in some areas outperformed the obsolete system. Identified differences were efficiently addressed and met the client’s requirements.

To prevent the need of manual intervention, within the program translation software, Seica implemented automatic adjustment of the edge positioning where required, with monitoring of such modifications. Both the legacy ATE and Valid System have test oriented languages with very similar structures. Digital test patterns, including logic states and timing information, are dealt with in the same manner and maintain a one-to-one correspondence. Valid System provides a friendly, user-oriented debug environment to ease validation of digital and analog test programs.The translation process, encompasses the obsolete test programs, and re-builds the Multi-Main structure to maintain operation on separate test modules.

Digital test debug takes advantage of the data acquisition memory of the channel cards and offers a very flexible logic analyzer capability across all I/O of the board under test. Modifications were promptly implemented and quickly back-annotated through incremental compilation. Diagnostic guided probe data can be verified, edited or learned from a reference node.

The process was extensively bench-marked for comprehensiveness, quality and overall advantages against alternative solutions. The verification was done against a complex digital board, migrating go no/go and guided probe diagnostics both via the LASAR/L2POST and the L2/XEC source paths. The full solution included a fixture adaptor to host the old fixtures and a conditioning harness to allow test and diagnostics at different temperatures.

For additional information on Seica Test equipment or to schedule a demonstration of the Seica Test equipment located at the American Competitiveness Institute, please contact Robert N. Berta; telephone at 610-362-1200 ext 253 or via e-mail at rberta@aciusa.org.



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