The traditional Transmit/Receive (T/R) module for an Active Electronically Steered Array (AESA) radar, or a transmit or receive module for any phased array antenna-based communications system, consists of an assembly of several chips per antenna element. There are typically thousands of elements needed for a single radar or communications antenna system. At the minimum, a Low Noise Amplifier, a Power Amplifier, a phase shifter, and a circulator are needed for the T/R module, usually with additional components such as capacitors, resistors, and inductors. Phased array antennas replace and vastly improve upon the legacy mechanically steered arrays, the moving dish or bar-type assembly commonly seen on older radar installations. Communications antennas benefit from the phased array in a similar fashion.

The EMPF is engaged in a ManTech effort, in partnership with Boeing (an IAB member company), to improve on the current stateof- the-art in T/R and other RF electronic modules by integrating the communications functions into a single chip, saving significantly by reducing component count for the module. The technology is scheduled to be inserted into the MMA (Multi Mission Aircraft) within NAVAIR and the DDG 1000 within NAVSEA. Future applications in the Navy such as U-CAS unmanned vehicles and others are also under consideration.

The single chip that is planned to take the place of several c omp o n e n t s on the module is a “system on a chip” or SoC. The semiconductor t e c h n o l o g y used to enable i n t e g r a t i o n into a single chip is SiGe or silicon-germanium. Chips made of this material can be fabricated using a semiconductor process known as Bi-CMOS which is much less expensive than the GaAs processing used to fabricate the MMIC (Monolithic Microwave Integrated Circuit) chips used in the RF assemblies today.

The SiGe chip will be mounted on an organic multilayer substrate using the principles of flip chip. Further cost will be saved by utilizing an organic based printed wiring board substrate instead of the expensive and heavy ceramic currently used. This packaging technique, known as Flip Chip On Board (FCOB), employs “bumps” that are applied to the chip I/O pads either by electroplating, evaporation, attachment of individual solder spheres, or by a technique called “stud bumping.” These flip-chip processes are shown in Figure 1-1. FCOB will be used to limit the parasitic effects of inductance and capacitance that would be incurred using the conventional wire bond interconnections most often used in modules for current phased array antenna systems. The EMPF will help select the process to be used for SiGe SoC.

For low volumes of bumps per month, such as are predicted for this application (relative to a commercial use), the stud bump is the least expensive way to apply bumps to a chip. In the stud bumping process, a ball bonder using gold wire, forms a ball bond on the pad of a chip and then is broken off. This leaves the ball bond attached to the chip pad as a bump that can be used in the flip chip process to connect the I/O pads of the chip to the bond pads of the circuit. Figure 1-2 shows a typical stud bump, as applied on the I/O pad of a chip using a standard ball bonding tool. The chip pad is roughly 4x4 mils (thousandths of an inch) and the ball is formed from 1 mil diameter gold wire.

The final assembly, using the FCOB method is shown in detail in Figure 1-3. The other types of bumps will be compared during this project by the EMPF. Since SiGe is inherently more compatible with future communications and radar applications that will operate at higher frequencies, the SiGe SoC modules will show improved performance over the currently use GaAs MMIC-based RF modules.

To summarize, the primary technology objectives driving the SiGe SoC material/packaging solutions are: • Better high frequency response • Lighter weight • Lower cost • Smaller devices The solutions being addressed by this ManTech effort at the EMPF, along with industry partners are to: • Develop Transmit and Receive RF Modules that utilize System On Chip (SoC) Silicon-Germanium Bi-CMOS technology. • Substitute lower cost SiGe for existing GaAs. • Utilize the SoC higher integration level to limit component count/module cost. • Utilize FCOB packaging technology to minimize cost while maximizing performance of phased array antennas. The partnership between the EMPF and Boeing on this ManTech project represents a typical arrangement to leverage the strengths and resources of both organizations on this critical technology development.