An integrated circuit chip is also called a die. This is because the chips are imaged, metallized, and processed in the form of a wafer of semiconductor material (usually single crystal silicon) that is later "diced" with a saw into a large number of individual chips, each one called a "die."

In most cases, each individual die is packaged into a plastic or ceramic package, such as a QFP (Quad Flat Pack), SOP (Small Outline Package), or one of the newer BGA (Ball Grid Array) or QFN (Quad Flatpack No-lead) packages. These packages are then soldered onto a PWB (Printed Wiring Board), usually along with other components, to make a PWA (Printed Wiring Assembly).

In addition to this normal type of assembly, there are two other ways of attaching a die to a PWA: Chip-on-Board (COB) and Flip-Chip-on-Board (FCOB). Figures 3-1, 3-2, and 3-3 show the three ways in which a die can be interconnected and attached to a PWB. There are basic similarities in the manufacturing operations for the die attach step in Figure 3-1, Standard Package Assembly and Figure 3-2, COB. The die is face-up in both the standard package and the COB direct attachment to the Printed Wiring Board. In contrast, for the flip chip die attach (as shown in Figure 3-3), the die must be flipped so that the face of the die, with its I/O connections, is turned toward the board.

The equipment for the standard package and COB methods of die attach are quite similar, having the capability to dispense or print the die attach adhesive and to place the face-up die onto the lead frame or the board. However, the equipment used for the flip chip die attach must also flip the chip over so that it is face down to present the electrical interconnection pads (bumps) to the substrate, with both an upward-looking camera to align the I/O pads and bumps on the die, and a downward looking camera facing the conductor pads on the board.

Most typical surface mount or die attach machines, however, are equipped only with a downward-looking camera that will align the edges of surface mount components and/or bare integrated circuit die with fiducials or other features of the lead frame or board. For flip chip die placement, this is usually augmented with an upward-looking camera to allow face down alignment of the flip chip pads with pads on the board. It should be noted that packages are sometimes made using flip chip for the interconnection of the die, but those packages are usually Ball Grid Array or Chip Scale packages in which the "lead frame" is actually a PWB. The purpose of this type of package, with flip chip as the die attach method, is to minimize the electrical capacitance and inductance (parasitics) associated with wire bonds. This method of die attachment is often used for microprocessors or ASICs (Application Specific Integrated Circuits) with very high I/O counts that have the need for very good signal integrity at very high signal speeds.

Equipment that uses either solder or adhesive die attachment materials, and methods for executing die attachment for standard lead frame-based packages, or for COB face-up applications, is available with various degrees of placement accuracy.

In fact, placement accuracy has improved within the last five years to +/- a few microns. For instance, many manufacturers are claiming 5 - 10 micron placement accuracy. For a premium price, accuracies down to +/- 1 micron are now available. These accurate die placement machines, combined with the most recent advances in wire bonding equipment allowing extremely accurate wire length, loop height, and loop shape control, allow COB with wire bonding to compete with flip chip in RF (Radio Frequency) applications where the accuracy of the parasitic reactances at each I/O pad of the die is a factor in the overall design. In applications such as this, the extremely precise die position, relative to other die in the assembly, defines an accurate bond wire length (and therefore resistance) and capacitance and inductance (wire loop control) that can become a predictable and reliable part of an RF design. Die attachment accuracy is now a formidable tool in such applications.

Some flip chip systems do not enable "self alignment" by utilizing the surface tension of liquid solder (molten solder bumps) to pull the die into alignment with the substrate pads. Those applications (using non-melting metal bumps) benefit because the original placement of the flip chip die can now be sufficiently precise so that no such "self-alignment" is required. Such a machine is shown in Figure 3-4. This machine is being used to flip chip die attach thousands of die per hour for an RFID (Radio Frequency Identification) Tag application. It has been shown to be suitable for silver bumped flip chip attachment in the EMPF Bumped RF Devices project.

As with die attach equipment, adhesive die attach materials (applied to adhere the die to the PWB or lead frame) are also undergoing a revolution. The EMPF is currently evaluating an academically developed nanoparticle silver-based die attach material for its potential uses in high power electronics, like those planned for the future DDG-1000 multi-mission destroyer. Because of its nanoparticle precursor, this silver paste becomes many times more thermally and electrically conductive than the solder materials usually used for this application. Upon sintering of the nanoparticles, thermal and electrical conductivities, many times higher than the solders or conductive epoxies that are traditionally used for this purpose, develop which approach those of metallic copper.

The benefit of the nanoparticle conductive silver paste is another area where flip chip improvements might be possible. This is particularly true in the area of thermal management for flip chip devices using solid metal bumps, where any type of solder attachment of the metal bumps forms a high thermal resistance solder layer at each I/O site. Attaching the flip chip using silver nanoparticle paste could potentially alleviate these thermal bottlenecks.

Die attachment, both in terms of equipment and materials, is only one of the many electronic packaging technology areas that hold opportunity for the constant improvement being pursued at the EMPF. Both the high power electronics being planned for DDG-1000, and the control electronics for GPS and IMU applications, will benefit from continued development of this technology.