A customer called into the EMPF Helpline because they observed shorting of a dual die transistor between pins
1 and 2 and between pins 4 and 5

The customer observed shorting of a dual die transistor between pins 1 and 2 and between pins 4 and 5, (source and gate on both die, Figure 2-1). Shorts between pins 1 and 6 and pins 2 and 6 were present (source and drain and gate and drain on die 1). The drains are located at pins 3 and 6.

Test Methods:

The failed transistor was provided by the customer and  removed from the assembly along with a tape section of good components. The pin to pin I-V characteristics for the failed and good transistor were confirmed with a curve tracer.  The good and failed transistors were soldered upside down (based upon the components wire bonding which was bottom side, refer to Figure 2-1) onto HASL coated copper coupons. They were then decapsulated using a controlled combination of fuming nitric and fuming sulfuric acid. The decapsulated components were examined optically and by SEM to determine evidence of the failure mode and mechanism.

Results:

• Based upon the component circuit diagram (technical data sheets), the substrate is tied to the source lead
  
  
• Based upon the X-ray imaging, the wire bonds were oriented from underneath (Figure 2-1).
  
  
• Curve tracer analysis indicated a short between the gate and source, drain and gate, and source and gate on Die #1. Die #2 showed a short between source and gate and drain and gate. Drain and source curves for die 2 appeared typical.
  
  
• The drains, gates and sources are identified in  Figure 2-2.
  
  
• Residual degraded encapsulant was present after extensive decapsulating steps indicating the material in this area was taken past its Tg (glass transition temperature), which is evidence of a thermal excursion (Figures 2-3 and 2-4).
  
  
• It was difficult to determine the presence of a specific failure mechanism (i.e. flash-over) because of the degraded residual encapsulant. However, die #1 does appear to be stressed based upon the cracked or wishbone appearance in the insulator layer areas where the degraded encapsulant resided (Figures 2-5 and 2-6).

Conclusions/Recommendations:

The shorts observed on the transistors are the result of an electrical overstress (EOS), most likely an over current scenario as indicated by the damage observed on the failed transistor. The cause of the EOS could be from a number of the following:

        1.  Use of the component outside of its recommended
            specifications.

        2.  No current limiting was designed into the circuit board to
            prevent a circuit load from damaging the assembly.

        3.  Transient voltages in the circuit that could cause short
            durations of currents above specifications.

The degridation of the encapsulant suggests an overcurrent senerio, over some extended period of time.

As part of failure mode analysis, the EMPF recommended examining the circuit application for possible sources of over voltage and over current. In addition, a review of the specification requirements/limits for the transistor in this circuit was also recommended.