A publication of the National Electronics Manufacturing Center of Excellence
June 2007

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American Competitiveness
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WEBSITE: www.empf.org

The EMPF is a U.S. Navy-sponsored National
Electronics Manufacturing Center of Excellence focused on the development, application, and transfer of new electronics manufacturing technology by partnering with industry, academia, and government centers and laboratories in the U.S

Technical Editor

Michael D. Frederickson,
EMPF Director

Please direct comments
and/or questions to the Editor at

In This Issue

Flip Chip Packaging for US Navy Electronic Systems


Wedge Bonding


Ask the EMPF Helpline!


Chip Scale Packaging


Integrated Passive Components


Tech Tips...Control of ESD Events in Flip-Chip, COB and CSP Manufacturing and Handling


Manufacturer’s Corner: Samsung SMT Assembly System


Upcoming Training Center Courses

Industrial Advisory Board
Gerald R. Aschoff, The Boeing Company
Dennis M. Kox, Raytheon
Gregory X. Krieger, BAE Systems
Edward A. Morris, Lockheed Martin
Jack R. Harris, Rockwell Collins
Gary Kirchner, Honeywell
Andrew Paradise, Northrop Grumman
Art Smedberg, ITT Industries, Avionics Division

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An electronic package for an integrated circuit (IC) die (chip) is defined as an enclosure or coating that physically protects the chip and its fragile wire bonds from the damaging effects of  handling and environmental stresses, such as moisture and chemicals, encountered during assembly and use (Figure 1-1).

Although the conventional package meets its physical requirements of mechanically protecting the chip, some electronic disadvantages arise from its use.  The wires used to interconnect the IC apply unwanted inductive and capacitive loads when the application requires operation at Radio Frequency (RF). This disadvantage, as well as the large area required to accomodate the long wires of the conventional package are mitigated by using the “flip chip” interconnection  method. The flip chip mounting process for an IC is shown in Figure 1-2.  Instead of wire bonds connecting the Input/Output (I/O) pads on the IC to a lead frame, each I/O pad has a “bump” made of solder, conductive epoxy, or even a “stud bump” made out of a short piece of bonding wire.  The chip is then flipped over so that its active surface is face-down toward the substrate circuit board and connected to the circuit using the metal or conductive epoxy “bumps.”  The short (usually only a few thousanths of an inch, or “mils”) interconnection of the bump has vastly lower inductance and capacitance than the long (ten to hundreds of mils) bond wires of the conventional wire bonded and glob-topped packaging.

In addition to the lower inductance and capacitance (termed “parasitics”) at RF frequencies and real estate savings due to elimination of long wires, another major advantage is the “area array” of I/O connections available in the flip chip method. Only “peripheral” I/O pads (pads at the perimeter of the chip) can be wire bonded. However, I/O pads can be designed onto the chip anywhere on the surface for flip chip attachment.  This gives flip chip a great geometrical (real estate) advantage over wire bonding in the number of I/O connections that can be placed on a chip, which results in smaller and less expensive chips. A lower cost can also be realized for designs that are limited to the number of wire bonds they can have by edge length. While there are dramatic advantages of flip chip due to the lower parasitics and more efficient real estate usage, there are definite issues with the technology as well.  The reliability of the conventional package, with its wire bonds, is well known and documented. However, flip chip reliability is very dependent on the physical behavior of the substrate to which it is attached.  Normally, the low cost plastic of a printed wiring board is a hostile environment for the typical flip chip.  Silicon chip material displays a coefficient of thermal expansion (CTE) between 2 and 4 parts per million (ppm), per degree Celsius (microinches per inch, per degree), while the typical epoxy circuit board CTE is 17 to 18 ppm.  Thermal stresses generated during temperature changes can be very large with such a large mismatch of CTE (see Figure 1-3).  For reliability, a flipped chip on a standard plastic circuit board generally requires “underfill”.  This is usually a silica-filled, low expansion, epoxy material used to stiffen the substrate and allow short bump interconnections of the flip chip to survive temperature excursions without the chip popping off the board.

Underfills have become extremely sophisticated and are used extensively for flip chips that are attached directly to plastic circuit boards with very impressive reliability.  The EMPF has studied underfills and used underfills for flip chips for our Navy ManTech customers. In fact, the combination of flipped test chips in the EMPF ManTech Electronic Miniaturization for Missile Applications (EMMA) project showed that such underfilled flip chips, attached to conventional plastic circuit boards, performed as good if not better than conventional packages when subjected to the  temperature cycling, shock, and vibration expected in a missile application. This flip chip mounting technique has greater advantage as the frequency of operation, or signal speed, increases.  In fact, some applications use flipped chips connected within Ball Grid Array (BGA) packages for the high speed electrical signals of microprocessor, microcontroller, or Field Programmable Gate Arrays (FPGAs) simply for avoidance of the parasitic inductance and capacitance of bonding wires. Of course, the underfilling process is an added manufacturing step, but the area array interconnection, size, and low parasitics advantages of flip chip over conventional wire bonded electronic packaging is sometimes enough to tip the scale in favor of the underfilled flip chip.

Flip chip has been investigated by the EMPF in several applications on Navy ManTech development projects. In addition to the EMMA program, the Monolithic Microwave Integrated Circuit (MMIC) Flip Chip ManTech program evaluated applications in an airborne radar that resulted in significant savings in size, weight, and manufacturing labor expense, benefiting the NAVAIR customer. Flip chip technology was again involved in the study of low cost, open system manufacturing of that radar in a follow-up ManTech project that investigated the automated multi-source manufacturing of such flipped MMIC chips. Currently, the EMPF is engaged in a unique application of a flip chip technology for the SiGe System on a Chip (SOC) application, planned for insertion on the DDG 1000 Zumwalt class destroyer.


Although flip chip technology currently represents a small segment  of the commercial electronics business, that segment  is growing where  the size, weight, and electrical performance advantages of flip chip can be effectively applied.  The EMPF and its partners will continue to advance manufacturing technology improvements utilizing flip chip technology for the benefit of Navy ManTech stakeholders in a variety of shipboard and airborne electronics applications.

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