In the acquisition of new combat systems for the U.S. Navy, the challenge is to meet operational requirements while reducing cost and minimizing risk.  System-on-Chip (SoC) is one solution to this challenge because it is a technology that includes the integration of all the necessary electronic circuits and parts for a system on a single integrated circuit (IC).  This single IC may contain digital, analog, mixed-signal, and radio-frequency (RF) functions all on one chip. 

The high integration levels offered by SoC can lower overall operating power, boost performance, and enable many new features not possible using standard components. This provides greatly expanded abilities compared to the performance limits of board-level systems based on off-the-shelf components.  Since there is no physical prototyping during SoC design, systems designs which include complex logic, signal processing, and high power components, must use accurate simulations to provide design verification.  Thus, the SoC Electronic Design Analysis (EDA) toolkits and design flows differ substantially from board-level design tools and flow.  SoC based designs have a technological advantage in the market if they are done efficiently, but this requires more planning and effort during the design process. 

SoC technology is currently being used by the EMPF in the Silicon Germanium System-on-Chip (SoC) ManTech project.  This includes development of transmit and receive ICs that will provide the capability to meet the low cost, weight and reliability requirements for phased array antenna solutions.  These antennas will be designed for operation in the Ku band, which is suitable for radar in both surface and airborne applications.  The EMPF, in partnership with Boeing (Phantom Works, Seattle, WA), will demonstrate manufacturability of the SiGe System-on-Chip devices, and the flip-chip-on-board (FCoB) interconnect technology suitable for use in Ku band radar antennas.  This combination of SoC with flip chip provides the parts reduction, space savings and cost reduction necessary to provide the solution required for new radars.  The reduction of the number of ICs and their size from the existing GaAs RF and Si logic radar circuit to a new single SiGe SoC radar circuit is shown in Figure 1-1.  This technology can also be extended to satellite communication applications since the architecture utilizes very similar RF cell design. 

Transmit/receive antennas have typically used GaAs chipsets. A key extension of this approach would involve the use of SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technology in lieu of more expensive GaAs. SiGe also offers the promise of higher levels of integration, combining the functions formerly accomplished by multiple GaAs chips plus a separate CMOS-based control chip onto a single SiGe Application -Specific Integrated Circuits (ASIC). Monolithic Microwave Integrated Circuit (MMIC) technology is a significant cost and size driver in phased array antennas, so this approach will help further reduce phased array antenna cost. This packaging approach is a revolutionary one based on the use of Chip-on-Board technology to provide a mass-produced solid-state replacement for the labor-intensive, heavy, and expensive traditional approach based on Multi-Chip Modules (MCM) and metallic waveguide structures. The packaging-related costs are anticipated to move downward over time, tracking well-established trends in the underlying technology. The use of SiGe for the ICs should also track similar established trends in the underlying semiconductor technology.

SiGe BiCMOS technology began manufacturing qualification in 1996 and has now completed at least 4 lithographic generations of development.  This technology integrates high-performance heterojunction bipolar transistors (HBTs) with state-of the-art CMOS technology.  Key technology characteristics for SiGe have been developed and are being used in current manufacturing processes with much success.  Each generation of the technology leads to smaller feature sizes resulting in higher speeds and lower power consumption.  When bipolar RF is integrated into the SoC with digital CMOS, this single chip solution allows up to 50mw of power savings through the elimination of intercommunication over the PCB. In addition to reducing power consumption, this integration also reduces cost (fewer pins) and PCB size (one chip instead of two), thereby significantly reducing the overall manufacturing cost. 

One of the most quoted figures of merit (FoM) is the cut-off frequency - fT of the HBT that increased from roughly 47 GHz in the 0.5 μm generation BiCMOS process to 210 GHz in the 0.13 μm process.  The enhanced performance, along with the decrease in size, are the driving factors that promote a reduction in both the number of ICs required and the area needed to perform the required RF functions.  Bipolar transistors give the speed required for the mixed and wireless applications, while the passives allow for the SoC integration, and the CMOS covers the logic requirements of the chip.  Digital signals are also less sensitive to line noise, which also drastically increases board layout flexibility and permits the analog RF to be optimally positioned adjacent to an antenna.  These improvements allow a decrease of the relative proportion of the RF area and more digital processing can be moved to the RF chip, enabling an integrated single chip solution.  These design reduction factors are critical for RF radar applications that involve phased array antennas.

A key to manufacturability of SiGe technology is the use of existing high-volume CMOS manufacturing processes. The maturity of process equipment, level of factory automation, wafer handling, yield management and quality assurance for continuous improvement make it possible to deliver high quality wafers in complex process technologies. For similar process complexity (measured by the number of critical photomask layers or the number of process steps), the manufacturing cost and fab yield are comparable regardless of the details of the technology.  The commitment to establishing a SiGe process within equipment capability makes it possible to deliver SiGe technology that is as repeatable and cost effective as mainstream CMOS.

In addition to the performance and die cost advantages that have promoted the growth of SiGe BiCMOS for RF transceivers, much lower product development costs are realized because of exponentially increasing cost of masks for each CMOS generation. Shorter time-to-market for SiGe BiCMOS products has been demonstrated because of the maturity of device modeling, the design platform, and the manufacturing capability that is possible when using well-established process modules and fab equipment.

The current Mantech project technology insertion improvement plans call for enhanced future performance and lower cost. The SoC and FCoB technologies enable use of low-cost Phased Array Antenna (PAA) architectures which will produce significant cost savings.  Cost savings of as much as 65% and weight savings of as much as 25%, compared to current phased array antenna technology, can be achieved using the FCoB approach based on the use of GaAs technology.  The use of SiGe technology can further reduce semiconductor chip-set costs by up to 90%.  In addition, the FCoB technology currently in development at Boeing is limited to 20 GHz due to the lattice spacing requirements and the size of GaAs chips necessary to perform the module functions.  SiGe has the potential to reduce the chip-set footprint, thus extending the practical frequency range for this architecture to 40 GHz or beyond.

In conclusion, the evolution of an RF transceiver from a set of chips tailored for each function and implemented in a variety of processes to a single, small, low power, low cost SiGe SoC chip has been the result of optimized process technology. This optimization has included integration of bipolar transistors with CMOS for low-power digital control and analog frequency synthesis.  The known solutions for scaling provide an opportunity for significant die size reduction using SiGe BiCMOS technology versus industry-standard CMOS technology. This die size savings can be translated into smaller packages, lower weight and  lower total cost depending on the level of analog and digital integration.  Product yield can also be improved, in conjunction with mixed-signal integration, due to the reduction in the number of interfaces between ICs.

REFERENCES:
Dunn, J.S. et al. Foundation of RF CMOS and SiGe BiCMOS Technologies. IBM J. Res. & Dev. Vol. 47, No. 2/3 March/May 2003
Leibson, Steven. Ready For The Jump to SOC Design. ECN Magazine. Tensilica, Inc.:12/15/05
Kempf, Paul. SiGe BiCMOS Plays a Growing Role in the Mobile Platform. wirelessdesignmag.com: Dec. 05
Kempf, Paul. Silicon-Germanium BiCMOS Technology. Jazz Semiconductor
Pawlikiewicz , Adam H. and David Hess. Choosing RF CMOS or SiGe BiCMOS in Mixed-Signal Design. www.rfdesign.com:3/1/06