Advanced RF devices, such as Silicon Germanium System on Chip (SiGe SoC) can be used in place of traditional RF components to lower overall operating costs, boost performance, and enable new capabilities. One key advantage of using Silicon Germanium in a System on Chip configuration is that an integrated circuit (IC) can be developed that contains digital, analog, mixed-signal, and RF functions on a single chip. An important application where SiGe SoCs can offer improvement is Phased Array Antennas (PAAs).
 
Phased Array Antennas (Figure 1-1) used by the Navy need to be made smaller, lighter, and more affordable. A Phased Array Antenna is constructed by arranging many small RF transmitting or receiving modules in an array. This enables the RF beam to be steered by controlling the phase of each individual module instead of mechanically steering a conventional RF antenna. The upper limit of the range of frequencies to which an antenna may be applied is limited by the spacing of the array. This in turn is limited by the size of the individual modules. A module constructed using a SiGe flip-chip system-on-chip package enables the implementation of Phased Array Antennas that operate beyond the 15-20 GHz currently possible with chip-on-board and gallium arsenide (GaAs) chipset technology alone. The EMPF is partnering with Boeing to demonstrate manufacturability of the SiGe System-on-Chip devices. The first phase of the ManTech project evaluates the component architecture, producibility of SiGe wafers, and packaging of die using flip-chip-on-board (FCoB) interconnect technology.

Test Cell Design
An initial step in the SiGe SoC design is to break up the circuit into test cells that facilitate testing of the individual components that will be used in the full system. SiGe test cells were created to properly assess the suitability of manufacturable SiGe technology for high-reliability RF applications. The test cells contain several variants of a particular device to determine which will optimum for the design. In addition to inductor designs, the test cells contain phase shifters, polarizer combiners, multiple amplifier designs, and other antennae supporting devices. During layout design, special attention was paid to developing a procedure that allows testing of the die that is sufficient to determine if parts are operable prior to packaging. The die was also designed with 32 daisy-chained flip-chip contacts around the periphery to support reliability testing of the flip chip interconnect scheme.
In order to limit costs, the SiGe fab runs were conducted sharing wafer real estate with other customers. These Multi-Project Wafers (MPW) were divided into 5mm x 5mm tiles enabling cost effective prototype runs. The tiles for this project were subsequently divided into 2.5mm x 2.5 mm test cells, 26 mils thick. Each test cell has four different architectures designed to test the various SiGe SoC devices. The test cells were designed with 3 mil pads and a 6-10 mil pitch.

Mounting Substrates
The FCoB uses, in this application, low temperature co-fired ceramic (LTCC) “boards” to be used for reliability testing and RF testing of SiGe test cell flip-chips and eventually will be the mounting substrate on which the SoC will be mounted. The LTCC ceramic has excellent RF properties and is suitable for RF applications where the practical frequency range can be as high as 40 GHz or beyond. The pads and traces used on the LTCC substrates are fabricated using thick film gold.

Packaging
Flip-chip packaging has many advantages in both cost and performance. High frequency RF components require low source impedances for both supplies and grounds. A comprehensive packaging study is being performed that evaluates the most suitable flip-chip interconnect technology for high-reliability RF applications. The study was designed to address the following areas in RF flip-chip packaging:

• Bumping technology
  
• Underfill material and process
  
• Environmental packaging
  
• Thermal expansion coefficient differences between SiGe die and the LTCC board.

Important to packaging design is the ability to create sufficient standoff height between the RF circuit and the ground plane on the substrate. This was needed to prevent RF field effects from affecting device performance. Based on computer models, a target of 3 to 5mils was established for a minimum standoff height. One major goal of the SiGe SoC packaging study is to understand the effects of the board’s ground plane on the SiGe device’s RF performance.

A detailed test matrix was constructed that included multiple attachment methods and materials. Only materials and processes that were robust, RF compliant, and readily available were considered for inclusion in the test matrix. The attachment methods considered were gold stud bump bonding, solder bump attachment, and diamond particle interconnect. Each process has its advantages and disadvantages.

Solder bumps are reworkable; failed die can be replaced after die removal, residual solder removal, fluxing and soldering of a new die. Solder bumps have a lower cost at high volume than stud bump bonding and uses standard soldering equipment; no thermal compression equipment required. Solder attachments also have a long history and demonstrated reliability and are well suited to high volume production. Solder bumps are not, however, well suited for fine pitch bond pads. They require fluxing, cleaning, and solderable under-bump metallization (UBM). Aluminum, standard pad metallization on SiGe die, is not a readily solderable surface, neither wettable nor bondable by most solders. Also, the cost of low-volume solder bump processing is more than the cost of low-volume stud-bumping.

Gold wire stud bumping of flip-chip packages is a cost efficient and popular packaging option for many applications, particularly those with smaller pad and smaller pitch requirements. For the SiGe SoC application, stud bump bonding is a robust packaging option given the process restrictions that must be overcome. The EMPF, Boeing, and Palomar Technologies (Carlsbad, CA) have developed a gold wire stud bumping process compatible with the requirements of the SiGe SoC flip-chip application. The process involves the use of single and triple-stacked gold wire stud bumps formed with 1 mil gold wire in conjunction with conductive adhesive (Figure 1-2). The use of triple-stack bumps increases standoff height which helps mitigate some of the expected strain induced by the SiGe die and LTCC substrate.

Another packaging option that is being evaluated is the use of a single gold wire stud bump in conjunction with a novel connection technology called Particle Interconnect. Particle Interconnect utilizes sharp, metallized, diamond particles which have been screened by size. These particles are attached to substrate contact pads, under bump metallization or other conductor surfaces using a standard electroplating process. The contact areas are defined with masks or through the use of an interposer. The embedded particles are sharp and create a “microbed-of-nails” that makes many parallel electrical contacts. The particles penetrate through oxide or other thin contaminants to make contact without a wiping or scrubbing action that is required for many other conventional contacts. Gold-wire stud bumped die are attached to the substrate using the particle interconnect technology and flexible interposer. Particle Interconnect (PI) has been shown to provide RF bandwidth greater than 65 GHz and a lifetime of greater than 30,000 insertions. Detailed information about particle interconnect can be found in the November 2006 edition of EMPFasis.

Currently, test cells are being RF tested to ensure functionality prior to packaging the devices. The RF test results are compared to the computer generated models that were used in the test cell architecture design. Following packaging, these tests cells and their various packaging methods will be environmentally tested.

Conclusion
While this phase of the Silicon Germanium System on Chip project focuses on test cell design and packaging, many lessons are being learned about SiGe manufacturability, modeling, and electrical characteristics. Throughout the design, manufacture, testing and packaging operations, the EMPF is evaluating each process and material to evaluate a top performing, low-cost high-frequency solution.