Current Navy ManTech projects are focused on affordability while providing superior performance. Through the application of advanced processes and technologies developed in military and commercial markets, the EMPF has improved new electronic systems for the Navy.  One of the methods used is the highly integrated, chip-level, electronics assembly process known as flip chip assembly and stud bumping.

Flip chip microelectronic assembly is the direct electrical connection of face-down (flipped) electronic components onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip bond pads. In contrast, wire bonding uses face-up chips with a wire connection to each pad. Flip chip components are predominantly semiconductor devices,, however, components such as passive filters, detector arrays, and MEMs devices are also used in flip chip form.

 IBM introduced flip chip interconnection in the early sixties for their mainframe computers and has continued to use flip chip currently. The assembly process has proliferated in many other applications, including automotive electronics, smart cards, RFID cards, electronic watches, cell phones, and high speed microprocessors. 

The popularity of flip chip packaging results both from flip chip’s advantages in size, performance, flexibility, reliability, and cost over other packaging methods, and from the widening availability of flip chip materials, equipment, and services. Eliminating package molding and bond wires reduces the required board area by up to 95%, and requires far less height. Flip chip offers the highest speed electrical performance of any assembly method and gives good input/output connection flexibility. Flip chip assembly is a mechanically rugged interconnection method when completed with an adhesive underfill. This method also is the lowest cost interconnection process for high volume automated production.

There are three stages in making flip chip assemblies: bumping the die or wafer, attaching the bumped die to the board or substrate, and in most cases, filling the remaining space under the die with an electrically non-conductive material. The conductive bump, the attachment materials, and the processes, differentiate the various kinds of flip chip assemblies. The most common bumping and attaching methods include solder bump, plated bump, stud bump, and adhesive bump. The bump serves several functions in the flip chip assembly. Electrically, the bump provides the conductive path from chip to substrate. The bump also provides a thermally conductive path to carry heat from the chip to the substrate. In addition, the bump provides part of the mechanical mounting of the die to the substrate. Finally, the bump provides a spacer, preventing electrical contact between the chip and substrate conductors, and acting as a short lead to relieve mechanical strain between board and substrate.

The cost, performance, and space constraints of the application determine which method is best. A current EMPF ManTech project is focused on the development of a silicon germanium (SiGe) System on a Chip (SoC) assembled in a Flip-Chip on Board (FCoB) configuration.  For SiGe applications, stud bump bonding is considered one of the most robust packaging options for the given process restrictions.


The Stud Bump Process

The gold stud bump flip chip process, bumps die by a modified standard wire bonding technique. This technique makes a gold ball by melting the end of a gold wire to form a sphere. The gold ball is attached to the chip bond pad as the first part of a wire bond. To form gold bumps instead of wire bonds, wire bonders are modified to break off the wire after attaching the ball to the chip bond pad. The gold ball, or “stud bump” remaining on the bond pad, provides a permanent connection to the underlying metal. Multiple bumps can be stacked to achieve an increased standoff to help mitigate some of the expected strain induced by the high thermal expansion mismatch between the chip and an organic substrate. The maximum number of bump stacks is recorded to be 17. However, 3-5 bump stacks are most practical. It is interesting to note that the total stack height is not directly proportional to the number of bumps stacked. That is, if the first bump is 40 microns high, the second bump stacked will compress the first bump deposited. Therefore, the total height will be less than 80µm, the sum of the two balls. An example is shown in Figure 1-1. The gold stud bump wire bonding offers a significant advantage because of the speed and low cost of the process. Current technology is able to achieve more than 16 bumps per second.

The gold stud bump process is unique in being readily applied to individual single die or to wafers. Gold stud bump flip chips may be attached to the substrate bond pads with adhesive or by thermosonic gold-to-gold connection. Die bumping and assembly services are available from several suppliers.

As previously described, one function of the bump is to provide spacing between the chip and the board. In the final stage of assembly, this under-chip space is usually filled with a non-conductive underfill adhesive, joining the entire surface of the chip to the substrate.  This underfill protects the bumps from moisture or other environmental hazards, and provides additional mechanical strength to the assembly. However, the most important purpose is to compensate for any thermal expansion difference between the chip and the substrate. Underfill mechanically bonds the chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps.

Types of substrates considered for attachment are organic (such as Rogers 4003 or FR-4), Low Temperature Co-fired Ceramic (LTCC), glass, or even silicon.

Typically, stud bumping requires the coining of the studs to reduce the wire tail produced and to produce bumps with consistent height. A normal coining tool can create height tolerances + 3-5 µm. Some manufacturers claim that lower tolerances (1.5 – 2 µm) on bump height are achievable using advanced equipment. A closed loop bonding process is utilized where high speed digital processing and rotary and linear control of X-Y movement allow for increased precision. Examples of stud bumps that have been coined are shown in Figure 1-2.

Conductive adhesive is the most common method for bump attachment to the substrate. Conductive adhesive is attached to the stud bump bottom by dipping the bumps into a pot (dob pot) containing the adhesive. The dob pots usually contain a flat surface (doctor plate) to ensure conformity of the adhesive volume.  The adhesive volume and bond line thickness are two conductive adhesive variables that need to be considered. Some experimentation is conducted in order to ensure proper post height and suitable reliability. Additionally, the conductive adhesive  must be selected. A fine pitch configuration also requires the adhesive to resist epoxy float which will displace the chip enough to cause misalignment or bridging.

Dobbed chips must be precision placed onto the substrate using flip chip placement equipment with an accuracy of + 10 microns or less. The placement force must also be optimized to ensure consistent post height.

Solder preforms are an alternative to the conductive adhesive attachment of stud bumps.  A small pad size may not allow sufficient opening in a stencil aperture to successfully screen print solder paste to the pads on the substrate. (The industry often uses a general three ball rule which maintains that the aperture opening should be greater than 3 solder balls in width. This would require a type 5 or 6 solder paste as shown in Table 1-3.

Also, eutectic tin-lead paste is vulnerable to gold embrittlement as it reacts with the gold from the stud bump and the thick gold deposit on the LTCC substrate. InAg (indium silver) and InPb (indium lead) are possible alternative solder paste candidates for fatigue resistant solder pastes to connect the gold bumps to the substrate.

Chips can then be reflowed using a conventional reflow or gravity oven. Air circulating convection ovens may cause chip movement and should be avoided. Some suppliers use a pulse heat reflow system that can apply pressure during curing. Typical conductive epoxies cure at approximately 130-170ºC.

Benefits and Advantages

1. Gold stud bumps have a conductivity advantage over tin-lead solder. Lead, and its alloys, have an electrical resistivity of 22 micro ohm-cm, while gold is 2.19 micro ohm-cm.
   
2. Gold stud bumps require no additional under-bump metallization (UBM). This reduces the costly step of masking and depositing UBM such as Electroless Nickel, Immersion Gold (ENIG) to the aluminum pads.
   
   

Conclusions

Gold stud bump processing is an increasingly popular technique for attaching advanced chips to a variety of substrates in order to achieve robust, low-cost, advanced packaging of highly integrated electronics. Using this technique in military applications is yet another means by which the EMPF supports the Navy ManTech affordability effort.