Recently, a customer contacted the EMPF helpline to request analysis of suspected electrical over stress (EOS) of their metal oxide semiconductor field effect transistor (MOSFET). The customer requested a Level 1 failure analysis of this transistor.

Response:
Level 1 failure analysis can be summarized as an “open and look” test of a failed component. The “open” part of the test consists of decapsulating the device to reveal parts and connections underneath the packaging. Next, the decapsulated device is examined by “looking” under the optical microscope and also with the scanning electron microscope. In addition, curve tracer analysis can be performed for electrical testing. For this customer, three failed transistors were removed from their respective assemblies by the customer. One failed transistor was generated by deliberately shorting the board. The others were failures discovered in the field. The EMPF recommended that both failed and virgin transistors be provided for the following tests in chronological order: microscopic examination, X-ray inspection, curve tracer analysis, decapsulation, and Scanning Electron Microscope (SEM) with Electron Dispersive Spectroscopy (EDS) analysis. The failures were confirmed by comparing the current-voltage (I-V) relationships of the failed and known good devices by curve tracer analysis.

Prior to decapsulation, there were several tests which provided information about the defective device. The simplest test was visual inspection which identified some defects immediately. Sometimes cracks can be seen by the naked eye, but the optical microscope provided a much clearer inspection. Any crack on the encapsulation surface indicated that the packaging had been compromised and was no longer effective. This type of inspection only provided information for external defects.

• The EMPF observed external cracks from package damage on two of the devices. (Figure 2-1)
  
• The third device was too severely damaged to perform electrical testing (Figure 2-2).

• Under inspection, the SEM showed evidence of a possible short due to EOS damage on the same decapped transistor (Figure 2-3).

Conclusions:
These transistors were suspected to have EOS failures by the customer. Level 1 analysis (“open and look” test) was requested by the customer. However, the EMPF could only electrically confirm such failures in two of the three devices. The other device had a damaged lead which could not be tested. The encapsulation cracks observed under the optical microscope suggest thermal stress. A possible explanation could be that the EOS caused the crack, or EOS could cause thermal stress to initiate the crack in the encapsulation. Evidence of possible EOS was also seen during SEM inspection. To prove the failure mechanism, Level 2 analysis would be required per customer’s request to isolate exactly where the EOS occurred. There are several possible scenarios for the EOS on two of the transistors.

• The component was not operated in its recommended specifications.
  
• The circuit was not designed to minimize or limit the current drawn by the assembly.
  
• Transient voltages could cause short periods of overload currents.
  
• Mechanical damage to the part which could lead to overload condition.
  
• Insufficient thermal contact of drain to heat sink, or poor heat transfer within assembly or housing.

Recommendations:
The EMPF recommended that the customer examine the circuit application for possible sources of overload in both voltage and current. Processing of parts should be investigated as well as the review of specification requirements and limits for the transistor in this circuit.

In addition, the EMPF can prove the failure mechanism by performing a Level 2 analysis. At this level, the approach will consist of all steps from Level 1 analysis as well as the following:

• Isolation of failure site
  
• Integrated circuit layer removal
  
• Root cause determination
  
• Corrective action analysis