The introduction of new packaging technologies and methods for their application, is one of the core competencies that the EMPF has endeavored to maintain as part of their mission statement. The training of both DOD and commercial personnel has also been an integral part of keeping our valued clientele informed on the latest developments in the arena of electronic manufacturing technology. The EMPF offers opportunities for engineers, scientists, technologist, and manufacturing personnel to take advantage of the wealth of technical knowledge that is available to them in the form of training classes that utilize the latest in equipment and material technology.

Each generation of new power components will be making the transition to smaller territorial footprints, decreasing power usage, and increasing circuit functionality. Chip scale modules, chip on chip, and system on chip designs are on the leading edge of meeting the requirements for future devices. The enabling technology necessary for the implementation of low power devices will also greatly depend on assimilating new passive designs as one of primary drivers for integration. The technology to incorporate passive components into package architectures offers benefits such as low noise and power consumption, as well as integrating baseband, memory, and RF features.

To take advantage system integrated designs, it is necessary to apply preventive measures to mitigate the parasitic effects of resistance and capacitance, which may be intrinsic to the integration of the various functions required. New Module designs now allow for low parasitics, High Q inductance, and an integration of digital and RF technology. New silicon on silicon flip chip designs offer densities of 7000 interconnects per Sq inch, with low inductance and increased signal speed. The CLC (chip-laminate-chip) model features signal characteristics that include buffer delay times of less than 3.5 nano-seconds and signal round trip of less than 500 pico-seconds, with no terminating resistors. The advantage of such packages are increased clock speeds and power savings.

Accompanying the versatility and capabilities of the new package designs, are innovative High Density micro-via PCB constructions, which contribute the enabling technology for the assembly of the low power package devices. The primary features of these substrates are an increase in I/O density, high speed, and low inductance characteristics. The substrate micro-vias are defined by laser ablation, which allows for via diameters of less than 25 microns with 50-75 micron pitch.

Additional advancements in nano-technology have now made possible material features that facilitate the requirements for high speed dielectric substrates (low DK < 3), low loss adhesives and resins, dimensionally stable laminates, and high thermal conductive interfaces. Assembly techniques will also have to be refined as the higher densities associated with low micro-power applications may require changes in both equipment and materials at the various stages of packaging. Reliability becomes a greater concern as the HDI assemblies undergo environmental stress testing. The compact nature of the packages and the reduced volume of solder will impose a greater amount of strain on the devices, making them more susceptible to fracture or separation. In many cases, the application of an interface with mechanically decoupling properties between the various packages will be needed to reduce the strain on interfacial joints. The application of underfills can mitigate the shear caused by the mismatch of material CTE (Coefficient of Thermal Expansion).

The EMPF offers a Chip Scale Packaging class which focuses on the manufacturing and application of small devices. The course covers various aspects of assembly from design to reliability, and includes the following topics:

• PCB Design
• Wire Bonding
  
• Die fabrication and assembly methods
• Inspection methods
  
• Handling supplier packaging
• Reliability
  
• Solder Paste printing
• Placement
  
• Attachment methods
• Reworking
  
• Cleaning
• Testing

Please contact the EMPF for further information on class schedules, and on custom designed classes for Chip scale packaging, and other available microelectronic classes. You can call the Registrar at (610) 362-1295 or email registrar@empf.org.