A publication of the National Electronics Manufacturing Center of Excellence
March 2008
ACI EMPF

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The EMPF is a U.S. Navy-sponsored National
Electronics Manufacturing Center of Excellence focused on the development, application, and transfer of new electronics manufacturing technology by partnering with industry, academia, and government centers and laboratories in the U.S

Michael D. Frederickson
EMPF Director

Barry Thaler, PhD., bthaler@aciusa.org
EMPF Technical Editor



In This Issue

Development of a Digital Receiver Exciter RF Architecture

 

Ask the EMPF Helpline!

 

Head on Pillow Defects on
BGA Assemblies

 

DoD Workforce Development

 

Manufacturer’s Corner: PACE

 

Tech Tips: Conformal Coating
Inspection

 

EMTC Course Schedule

 

EMTC Online Registration

IAB
Industrial Advisory Board
Gerald R. Aschoff, The Boeing Company
Dennis M. Kox, Raytheon
Gregory X. Krieger, BAE Systems
Edward A. Morris, Lockheed Martin
Jack R. Harris, Rockwell Collins
Gary Kirchner, Honeywell
Andrew Paradise, Northrop Grumman
Art Smedberg, ITT Industries, Avionics Division


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title

 

Today’s digital radars are designed to provide optimal performance in support of multiple simultaneous missions. As technology evolves, so must capability, and thus next generation radars must provide increased dynamic range and bandwidth in support of new capabilities.

Current REX downcoverter designRadars using open architecture distributed structure at each sub-array are considered instrumental and necessary for achievement of this kind of unprecedented performance in the presence of jamming and clutter. In order to incorporate open architecture into these radars, development of digital receiver and exciter (DREX) subsystems is essential. Digital array radars require many DREX subsystems in order to support performance needs.

Reduction in size of hardware is essential in the implementation of DREX technology, as many radars contain hundreds to thousands of sub-arrays, each requiring at least one DREX subsystem. Obviously, size, cost, and weight immediately become a huge focal point of concern. In most cases, the minimization of size, cost, and weight of a subassembly must also be traded with form, fit, and function of whichever existing receiver exciter (REX) technology that is to be replaced.

Fabrication and assembly processes must also be developed in support of a low-cost DREX for distributed architecture antenna sub-array. Key trade studies in support of this development shall focus on design, fabrication and packaging options. Optimal use shall be made of readily available, low cost, commercial off-the-shelf (COTS) and military off-the-shelf (MOTS) subsystems and components in the design trades.

Present REX assemblies in the higher frequency ranges, such S-Band, use high performance connectorized component packages to meet requirements (Figure 1-1). Increased volume and weight in addition to the higher costs associated with connectorized packages, cables, and specialized assembly are all undesired aspects of present REX technologies. Surface Mount Technology (SMT) can lead to significant savings in size, weight, and cost. While UHF DREX assemblies using SMT technology have been proven to be cost effective, achieving similar results at higher frequencies requires improved performance from the functional component packages and interconnecting substrates. One goal of a new REX design would be to fully model and optimize the characterization of the RF performance of the DREX assembly. New package configurations and tight control of assembly features must be equally developed to achieve repeatable RF performance at high frequency bands. Additionally, particular attention to the SMT process must be considered to ensure assembly yields for new package features and for achieving acceptable product reliability.

Established and innovative DFM (Design for Manufacturability) techniques can be employed to help achieve a high-yield surface mount DREX downconverter design. The DFM task would give the DREX more robust manufacturability by improving functional yield, reducing cost and increasing the reliability of the modules. Design for testability (DFT) methods should also be integrated into the DREX design review to ensure that certain testability features are included in the hardware product design.

Another important trade study necessary for a DREX design is the development of fabrication and assembly processes to extend current surface mount technology to the desired frequencies. Mulitilayer printed circuit boards incorporating microwave compatible materials would be utilized to develop processes capable of providing the required etching tolerances and parts placement accuracies. A top level functional manufacturing process flow would also need to be established, detailing the fabrication steps that accommodate a number of SMT package styles. Materials, such as ceramic and PTFE-based materials for microwave/RF functionality, and FR4 and polymide for non-RF functions, should be taken into consideration. Blind vias, buried vias, standard vias, and via-in-pad for BGAs should also be evaluated within some trade space. The use of materials compliant with Restriction of Hazardous Substances (RoHS) regulations should also be considered, depending on the application. The EMPF has been a leader in providing technical expertise regarding lead-free strategies to industry for years. Additionally, reliability and quality management would need to be addressed for the SMT components.

Cost reduction goals are envisioned from the use of SMT techniques on microwave/RF quality multilayer circuit boards to integrate module and MMIC circuit functions. Processes would need to be developed for the assembly of the DREX modules which will involve a high level of automation to reduce assembly costs and deliver a consistent high level of quality complying with J-STD-001 class III requirement. Additionally, evaluation of available component packaging options must be performed, for components used in conjunction with RF signal bearing substrates. The packaging study should investigate reliable integration of components in the DREX substrate, utilization of integrated passive devices, robust flip-chip attachment methods, high frequency compatible underfill materials, reliability of RoHS compliant materials, and packaging / substrate testability.

Conceptual DREX downconverterOnce the aforementioned trades are concluded and evaluation is complete, fabrication of a SMT prototype (Figure 1-2) can enable demonstration of the technology transition. A comprehensive cost model of the DREX module must also be developed, in order to minimize the cost-size-weight-and-power figure of merit upon completion of the project. The target process goal should be to reduce cost per DREX module by around 50%. The EMPF could contribute to the development of a low-cost DREX module in areas of:

  • Flip-chip die bonding capability
  • Evaluation of low underbody clearances on miniature components, and associated cleaning challenges
  • X-Ray inspection to guarantee compliance to J-STD-001 class III requirements
  • Solder paste printing
  • Impact of RoHS compliance on fabrication processes

In order to identify areas of improvement, the DREX SMT downconverter can be simulated, targeting process optimization, cost reduction, and process flow volume. These simulations are designed to identify process bottlenecks, perform producibility risk analysis, perform plan versus actual schedule analysis, and facilitate supply chain collaboration.


Nick Fardella - Packaging Engineer


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