Chip scale packaging (CSP) is a very eclectic technology with a diversity of designs and fabrication techniques. The nomenclature is often confusing and synonymous with other common chip and wafer level technologies associated with the miniaturization of electronic packages. The “technical” definition can be loosely described as a packaging device that approximates 1.5 times the area of the active die, but there are many factors that contribute to the construction of the CSP. Typical packages are relatively low in profile, and can include both leaded devices such as QFPs (Quad Flat Packs) or BGA (Ball Grid Array) types such as FBGAs (Fine-Pitch BGAs), to give an example. New innovative technologies feature die stacking designs and 3D platforms that vertically integrate multi-functional dies, such as memory or processing, on the same CSP. Die platform technologies have advanced to offer a multiple choice of integration constructions that are cost effective and performance driven. The EMPF has been actively engaged in the research of various CSP technologies, and has been involved in integral parts of design, materials, assembly, and reliability testing of the various package platforms. Some will be potentially applied in high end DOD applications. The reliability of the CSP will often determine the platform technology used for specific applications. Table 6-1 below illustrates the various comparative attributes of each CSP device.

Reliability essentially depends on the type of device used in the CSP construction. BGA devices can utilize either wire bonding or flip chip as a method of attachment. Both have divergent responses to environmental stress testing, where the failure mechanisms differ in nature. Reliability for wire bonding packages focuses on the integrity of the wire and the interfacial intermetallic, formed by the metals used in the bonding process. This can affect the structural reliability of the wire bond, and eventually cause degradation of the joint. Another primary reliability concern for an aluminum and gold interface can be observed in the breakdown of electrical performance, resulting from the diffusion of the two metals at higher processing temperatures. The consequence of the diffusion is the initiation of Kirkendahl voids that may cause open areas to occur in the wire bonding interface.

Flip chip and BGA devices that use solder balls as a means of attachment, rely more heavily on minimizing the strain caused by materials with incompatible coefficients of thermal expansions (CTE). In case of micro BGAs, the CTE mismatch causes excessive strain on a smaller volume of solder. Through careful selection of substrate materials and underfills, and by mechanically decoupling interfaces, the shear stress caused by mismatched CTE can be mitigated. Recent projects undertaken by the EMPF, have observed that CTE, location of the device, and elastic modulus of the adjacent materials, will determine where the stresses are predominately distributed. A proportional balance of elastic modulus and CTE is important to minimize fracture in the die area, or delamination in the package substrate. Figure 6-1 shows an example of where the typical stress points are located on a BGA.

The EMPF has a well equipped demonstration facility and has constructed a course that will educate, inform, and demonstrate many of the techniques used in the manufacturing of chip scale packages. The topics and labs include:

• Package Types
• Placement
  
• PCB Designs
• Attachment Methods
  
• Wire Bonding
• Handling and Packaging
  
• Die Fabrication
• Inspection and X-Ray and Assembly
• Reworking
  
• Solder Paste Printing • Reliability

The EMPF also offers customized versions of the CSP class which can be tailored to the needs of the customer. For more information on CSP classes, please contact the Registrar at 610-362-1295 or email registrar@empf.org.