A publication of the National Electronics Manufacturing Center of Excellence
September 2008

ISO 9001-2008
American Competitiveness
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WEBSITE: www.empf.org

The EMPF is a U.S. Navy-sponsored National
Electronics Manufacturing Center of Excellence focused on the development, application, and transfer of new electronics manufacturing technology by partnering with industry, academia, and government centers and laboratories in the U.S

Michael D. Frederickson
EMPF Director

Barry Thaler, PhD., bthaler@aciusa.org
EMPF Technical Editor;
Technical Editor, Empfasis

Carmine Meola, cmeola@aciusa.org
Factory and Training Services

In This Issue

Flip Chip Assembly


Ask the EMPF Helpline!


Advanced High Power,
High Density Connectors


Manufacturer’s Corner:
Manncorp SMT Line at EMPF


Tech Tips: Reflow Experiment


Failure Analysis


Upcoming Training Center Courses


EMTC Online Registration

Industrial Advisory Board
Gerald R. Aschoff, The Boeing Company
Dennis M. Kox, Raytheon
Gregory X. Krieger, BAE Systems
Edward A. Morris, Lockheed Martin
Jack R. Harris, Rockwell Collins
Gary Kirchner, Honeywell
Andrew Paradise, Northrop Grumman
Art Smedberg, ITT Industries, Avionics Division

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The intense competition in the electronics industry generally serves to drive down the size and cost of electronic products while improving their performance, flexibility, and reliability. As a part of this effort, packaging methods are constantly being improved and new, innovative methods are being developed. One area of focus is highly integrated chip-level electronics assembly, using multiple unpackaged dies and electrical components in a single package. One of the most popular methods is known as flip chip assembly.

Flip chip microelectronic assembly is the direct electrical connection of face-down, or flipped electronic components onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip input/output (I/O) pads. In contrast, wire bonding uses face-up chips with a wire connection to each pad (Figure 1-1).
Flip chip components are predominantly semiconductor devices; however, components such as passive filters, detector arrays, and microelectromechanical systems (MEMS) devices are also used in flip chip form. IBM still uses the flip chip interconnection that they introduced in the early sixties for their mainframe computers. The assembly process has proliferated in many other applications, including automotive electronics, smart cards, radio frequency identification (RFID) cards, electronic watches, cell phones, and high speed microprocessors.

The popularity of flip chip packaging results both from flip chip’s advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the increased availability of flip chip materials, equipment, and services. Eliminating package molding and bond wires reduces the required board area by up to 95%, and requires far less height. Flip chip offers the highest speed electrical performance of any assembly method due to reduced signal inductance.

This is because the interconnection path is much shorter in length (0.1mm versus 1-5mm) greatly reducing the inductance of the signal path. Additionally, the power to ground inductance is reduced. By using flip chip interconnection, power can be brought directly into the core of the die, rather than having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon. This is a key factor in high speed communication and switching devices and gives good I/O connection flexibility. A higher signal density is available with flip chip assembly. The entire surface of the die can be used for interconnect, rather than just the edges. Since a flipped chip can connect over the surface of the die, it can support vastly larger numbers of interconnects for a given die size. For a die where size is determined by the edge space required for bond pad (“pad limited”) the size of the die can be reduced, saving silicon cost. In some cases, the total package size can be reduced using flip chip. This can be achieved by either reducing the die to package edge requirements, since no extra space is required for wires, or in utilizing higher density substrate technology, which allows for reduced package pitch. Flip chip assembly is a mechanically rugged interconnection method when completed with an adhesive underfill. This method also has the lowest cost interconnection for high volume automated production.

There are three stages in making flip chip assemblies: bumping the die or wafer, attaching the bumped die to the board or substrate, and in most cases, filling the remaining space under the die with an electrically non-conductive material. The conductive bump, the attachment materials, and the processes used differentiate the various kinds of flip chip assemblies. The most common bumping and attaching methods include solder bump, plated bump, stud bump, and adhesive bump. The bump serves several functions in the flip chip assembly. Electrically, the bump provides the conductive path from chip to substrate. The bump also provides a thermally conductive path to carry heat from the chip to the substrate. In addition, the bump provides part of the mechanical mounting of the die to the substrate. Finally, the bump provides a spacer, preventing electrical contact between the chip and substrate conductors, and acting as a short lead to relieve mechanical strain between board and substrate.

The cost, performance, and space constraints of the application determine which method is the most suitable. A current EMPF project is focused on the development of a silicon germanium (SiGe) System on a Chip (SoC), assembled in a Flip Chip on Board (FCoB) configuration. For SiGe applications, stud bump bonding is considered to be one of the most robust packaging options given the process restrictions. The balance of this article reviews some of the more common bump attachment methods.

Solder Bump Flip Chip
The solder bumping process first requires that an under bump metallization (UBM) be applied to the aluminum chip bond pads, typically by sputtering or plating to remove the insulating oxide layer and to define the solderable area. Solder is deposited (Figure 1-2) on the UBM by needle-depositing or screen printing solder paste, evaporation, or electroplating. After solder bumping, the wafer is cut into bumped die. The bumped dies are placed on the substrate pads, and the assembly is heated to make a solder connection.

Stud Bump Flip Chip

The gold stud bump flip chip process, bumps die by a modified standard wire bonding technique. This technique makes a gold ball for wire bonding by melting the end of a gold wire to form a sphere. The gold ball is attached to the chip bond pad as the first part of a wire bond. To form gold bumps instead of wire bonds, modified wire bonders break off the wire after attaching the ball to the chip bond pad. The gold stud bump remaining on the bond pad provides a permanent connection through the aluminum oxide to the underlying metal. Gold stud bump flip chips may be attached to the substrate bond pads with conductive adhesive (Figure 1-3) or by thermosonic gold-to-gold connection.

Plated Bump Flip Chip
Plated bump flip chip uses wet chemical processes to remove the insulating oxide layer and plate conductive metal bumps onto the wafer’s aluminum bond pads. In general, plated nickel-gold bumps are formed on the semiconductor wafer by electroless nickel plating of the aluminum bond pads of the chips. After plating the desired thickness of nickel, an immersion gold layer is added for protection, and the wafer is cut into bumped die. Alternatively, silver bumps are electroplated on a sputter seeded semiconductor wafer (Figure 1-4). Attachment generally is by solder or adhesive, which may be applied to the bumps or the substrate bond pads by various techniques.

Adhesive or Polymer Bump Flip Chip
The polymer bump process is a patented, stencil printing technology in which isotropically conductive, silver filled polymers are printed through metal stencils to form polymer bumps on a zincate-nickel gold, electroless plated UBM that covers the aluminum bond pads of the semiconductor die. The polymers are either thermoset which cures with heat, or thermoplastic which softens with heat. These silver-filled polymers are formulated for high precision stencil printing through laser etched or electroformed metal stencils. Once the bumped wafers are diced, the chips are inverted and bonded to the substrate. Final processing involves a heat cure for the thermoset bumps while the thermoplastic bump connections are made in a few seconds as heat and pressure are used to melt the thermoplastic.

Flip Chip Underfill
As described above, one function of the bump is to provide a space between the chip and the board. In the final stage of assembly, this under-chip space is usually filled with a non-conductive “underfill” adhesive joining the entire surface of the chip to the substrate.

The underfill protects the bumps from moisture or other environmental hazards, and provides additional mechanical strength to the assembly. However, its most important purpose is to compensate for any thermal expansion difference between the chip and the substrate. Underfill mechanically “locks together” chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps.

Underfill may be needle-dispensed or jet-dispensed along the edges of each chip. It is drawn into the under-chip space by capillary action and heat-cured to form a permanent bond.

The methods covered in this article are only a few of the wide range of techniques used as part of the flip chip process. The development of new techniques is proceeding continually. Flip chip assembly has been shown to have significant advantages over other microelectronic packaging methods. Several varieties of flip chip assembly, including solder bump, plated bump, gold stud bump, and adhesive bump are suitable for a wide range of applications.


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