A publication of the National Electronics Manufacturing Center of Excellence
September 2009
ACI EMPF

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WEBSITE: www.empf.org
www.aciusa.org

The EMPF is a U.S. Navy-sponsored National
Electronics Manufacturing Center of Excellence focused on the development, application, and transfer of new electronics manufacturing technology by partnering with industry, academia, and government centers and laboratories in the U.S

Michael D. Frederickson
EMPF Director

Barry Thaler, PhD., bthaler@aciusa.org
EMPF Technical Editor



In This Issue

Advanced Packaging of SMTAssemblies for Greater Cost Reduction

 

Ask the EMPF Helpline!

 

Fixturing for Selective Soldering

 

Tech Tips: Battery Selection

 

Manufacturer’s Corner: KIC

 

Electronics Manufacturing Boot Camp

 

EMTC Online Registration

 

Upcoming Training Center Courses

IAB
Industrial Advisory Board
Gerald R. Aschoff, The Boeing Company
Dennis M. Kox, Raytheon
Gregory X. Krieger, BAE Systems
Edward A. Morris, Lockheed Martin
Jack R. Harris, Rockwell Collins
Gary Kirchner, Honeywell
Andrew Paradise, Northrop Grumman
Richard Kidwell , ITT Industries


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title

Legacy electronics assemblies, such as through-hole (Figure 1-1) and connectorized component packages, are robust and prevalent throughout industry. However, each of these assembly methods have reached their limits in terms of weight, volume, reliability, and most importantly cost. With cost reduction of assemblies now the primary focus area throughout the electronics industry, there is more of a need than ever to implement the latest advancements in surface mount technology (SMT) into electronics assembly designs. Although SMT has been utilized in the electronics industry for many years, implementation of the technology is still in the ever-evolving process of reducing component footprint size, component spacing, and component I/O pitch. Implementation of the most up-to-date SMT processes provides optimal weight, volume, and cost savings, for any type of assembly.

The use of SMT components in electronics assembly designs significantly minimizes real estate on a printed circuit board (PCB). SMT components are significantly smaller than their standard through-hole, or leaded, component counterparts. They can be one-quarter to even one-tenth of the size and weight of a leaded component. Since SMT components are attached using small solder joints, they must be small and lightweight. Smaller component size means smaller component footprint, and less occupied PCB real estate. This results in much greater circuit densities. Figure 1-2 shows an example of an assembly using SMT. The resistors and capacitors occupy considerably less real estate than those shown in Figure 1-1.

SMT components also allow for denser routing within the internal PCB layers. In the case of through-hole PCBs, any circuitry on internal layers must be routed around the through-holes, adding complexity to the design. Internal circuitry of a SMT PCB doesn’t have the through-hole restrictions, so traces can be routed with higher density. Likewise, a lack of through-holes allows for the capability of mounting more components on the backside of the PCB. Increasing the circuit density of the PCB results in a significant size reduction of the assembly, as great as four times smaller, with lower material costs. Additionally, SMT components can cost around one-half to one-quarter to that of its leaded counterpart. The savings are even greater when compared to connectorized packaged components, which also require connectors and cabling as their interconnects. This is especially compelling data for assemblies that contain many individual components.

Surface mounting of components lends itself to a high degree of automation. Traditional leaded component assemblies require a great deal of touch labor. Automation of PCB assemblies limits touch labor to automation set-up. Automation reduces labor costs and greatly increases production rates. These improvements could result in a cost savings of 25 percent or better. For SMT components with very small case sizes, a certain level of manufacturing process development may be necessary to assure parts placement accuracy. Additionally, a top level, functional manufacturing process flow may also need to be established in order to detail the fabrication steps that accommodate a number of SMT package styles.

The leads and cables in leaded component and connectorized package assemblies contribute a certain amount of inductance, potentially degrading the performance of the assembly. Since SMT components are virtually lead-less, the amount of inductance added at the solder joint is considered negligible, and therefore contains far less parasitic losses and potentially less consumed power. This would provide savings at the higher system level. The lack of leads or cables in an SMT assembly also provides much better reliability. Since SMT components are attached by a single solder joint, rather than multiple leads or wires, and have much smaller mass than their counterparts, they provide much better shock and vibration resistance. Thus SMT assemblies exhibit higher yields than their leaded assembly counterparts, and are far less likely to require repair in the future. Likewise, greater yields directly contribute to cost savings.

Advanced packaging using SMT can provide even greater cost, weight, and size savings. System-on-Chip (SoC), Flip-Chip-on-Board (FCoB), System-in-Package (SiP), and System-on-Package (SoP) are examples of SMT advanced packaging methods, each designed to help provide such savings. SoC refers to integrating many components of an electronic system into a single integrated circuit or chip. The SoC may contain digital, analog, mixed-signal, and RF functions, all on a single device. Flip-chip technology (Figure 1-3) takes SoC to the next level by eliminating the integrated circuit (IC) package and bonding the bare die directly to the PCB. Flip-chip eliminates the need for wirebonds,
further reducing the device’s footprint size.

As the complexity of circuit functionality continues to grow, so does the number of elements within the circuit. This presents great challenges in attempting to incorporate the added functinality onto a single SoC. Implementation of SiP helps surpass certain limitations of SoC capabilities, by allowing for integration of many functions into a single package. SiP (Figure 1-4) integrates one or more SoCs, or other ICs, along with discrete components, using lateral and even vertical integration technologies. The ICs within a SiP can also be stacked, as another means of adding functionality of a circuit, while minimizing the footprint of the package. The stacking of die, or chip stacking (Figure 1-5), deviates from the traditional two-dimensional means of attachment, and involves utilization of the third, or “z” dimension.

SoPs take SiPs a step further, by incorporating multiple dissimilar components and materials, such as silicon, gallium arsenide (GaAs) and silicon germanium (SiGe), as well as passives, into a single package. SoPs can utilize systems-on-chips (SoC) for IC integration, along with SiP, multi-chip module (MCM) and 3D chip stacking techniques for highly-integrated package integration.

Advanced packaging using SMT provides design flexibility in achieving manufacturing design goals. The EMPF has proven success in design and manufacturing of SMT assemblies. More information can be found by visiting the EMPF website, www.empf.org, or by calling the EMPF technical staff at 610.362.1320.


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