The demand for smaller, faster, and lower cost electronics has led the electronics industry move to higher density interconnects. The trend of electronics miniaturization, both in consumer and military applications, challenges board assembly materials, processes, and reliability. This trend has led to the interconnection of bare die, rather than packaged devices, to the circuit board or substrate.

There are many challenges that package designers encounter such as high frequency applications, thermal management, and stress due to coefficient of thermal expansion (CTE) mismatch. Impedance of the signal lines on the packages, cross talk noise between these lines, inductance of the interconnects, placement of decoupling capacitances on the chip, in the package, and on the printed circuit board (PCB) must all be considered when designing for high frequency applications. Managing thermal requirements with limited space inside a system and a growing chip power also presents a difficult challenge.

When selecting packaging methods, cost, form factor, and performance are the key drivers. Applications such as cellular telecommunications, ground based GPS receivers, unmanned aerial vehicle (UAV) cameras (Figure 1-1), radar antennas, and wearable portable consumer electronics often require the use of flip-chip packaging for its small form factor and, in some cases, high speed. In other cases (typically with I/Os in the range of 100-600), the existing infrastructure, flexibility, and the material/substrate costs of wire bonding provide dominant advantages.

For example, the total cost for a wire-bonded package with less than 600 I/O is typically less than an equal area flip-chip package. For a high-volume application, the chips are designed and the die size is minimized to take advantage of flip-chip’s efficient use of silicon real estate, so that a wafer yields many more flip-chip die. The resulting die cost reductions can significantly lower the total cost per flip-chip package below that of the comparable wire bonded package.

Other packaging methods are available for integrated circuit (IC) interconnects. Package cost, device performance, and overall size determines the choice of packaging options. Surface Mount Technology (SMT), Package-on-Package (PoP), Flip Chip, and Wire Bonding each have their advantages and disadvantages. Trade-off studies need to be considered before pursuing a packaging method.

Wire Bonding
Wire bonding is a method of making electrical connection between an IC and the external leads of a substrate using very fine bonding wires. Wire bonding can also be used to connect an IC to other electronics or to connect from one PCB to another. Wire bonding is cost effective, flexible and is used to assemble the vast majority of semiconductor packages. The most common bonding processes are ball bonding and wedge bonding. Gold wire is typically used for ball bonding while gold or aluminum wire is typically used for wedge bonding. In both processes, a combination of heat, pressure, time, and ultrasonic energy are required to make a connection.

Flip Chip
Flip Chip packaging eliminates the use of wire bonds to make a direct electrical connection of electronic components onto substrates, circuit boards, or carriers. Connections are made by using conductive bumps on chip bond pads and “flipping” the chip onto the external circuitry (so the top side faces down with its pads aligned with matching pads on the external circuitry). The conductive bumps are directly connected to the substrate after which the flip chip, in most cases, is underfilled with electrically insulating adhesive to provide additional mechanical support. Flip Chip on Board (FCoB) is advantageous for a variety of applications requiring greater performance, flexibility, and reliability, with a reduction in overall size and cost (depending on the quantity and the complexity of the design).

3D Packaging
PoP and PiP (Package-in-Package) are members of the 3D stacked die packaging family. 3D packaging, as seen in Figure 1-2, provides a functional integration in conventional packaging families by stacking die, stacking packages, or a combination of both, and using several assembly methods such as wire bonding, flip chip, and surface mounted components. In PoP and PiP bare die and other devices are connected to substrates or interposers, which are then vertically stacked on top of one another and interconnected together. Often, the stack is placed on top of a fine pitch ball grid array (FBGA) base and interconnected to it. After all internal connections have been made, the package is overmolded into a chip scale package (CSP). The vertical stacking significantly reduces the package footprint. This technique allows discrete logic and memory ball grid array (BGA) packages to be combined vertically. The memory package is typically placed on top of the logic package due to the larger number of BGA connections.

In each packaging method, cost comparisons and analyses are greatly dependent on modeling conditions and correlate to the choice of substrate technology. Substrate choice is often dependent on production volume and other considerations.

In the future, new technologies such as optical interconnects and wafer level packaging (Figure 1-3), as well as advances in current technologies, will continue to redefine electronics packaging solutions for future applications.

References:
1. White Electronics Designs Corporation. <http://www.whiteedc.com/>.
2. Elenius, Peter, and Lee Levine. “Comparing Flip-Chip and Wire-Bond Interconnection Technologies.” Chip Scale Review July/August (2000). <http://processsolutionsconsulting.
com/pdf/Flip_Bump/csr-7-00.pdf>.
3. STATS ChipPAC. <http://www.statschippac.com/services/packagingservices/3dsdsp.aspx>.
4. Leaded Surface Mount Technology. Packaging Databook, 2000. Intel. <http://www.intel.com/assets/pdf/pkginfo/ch_07.pdf>.