Failure analysis of components and integrated circuits requires specialized equipment and knowledge of cause and effect relationships to discover how and why failures occur. Performing the correct tests in the proper sequence is critical to determining the cause of a failure without removing vital evidence. Failure analysis conclusions should include objective recommendations for corrective actions. This is a requirement of the ISO9000 quality system, which most companies adhere to. It may not always be possible to pinpoint the cause of failure in a component, but thorough recording of all details and findings can still help to eliminate possible causes and focus attention on those areas that may be the most effective in correcting the problem. For failure analysis to remain successful, laboratories must remain well equipped with both cutting edge equipment and a stored wealth of knowledge and experience from employees, books, periodicals, and company findings that can be accessed by everyone involved.

Failure analysis (FA) capability supports the development of semiconductor technology and packaging. Failure analysts need new techniques and advanced equipment to match the rate of Moore's Law so that problem solving can remain efficient and accurate. Moore's Law is the observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors per square inch on integrated circuits has doubled every year since the integrated circuit was invented. The International Technology Roadmap for Semiconductors (ITRS) [1] is a good source of information for emerging trends in device size, speed, power, and other indicators as determined by the Technology Working Groups in ITRS (Table 1-1).

Yearly studies indicate evidence of many challenges looming in the near future for failure analysis. These challenges are in the areas of fault isolation, inspection, and de-processing. As technology progresses, fault isolation continues to be the most important area to focus on. It is in this area where the ultimate cause of failure is typically found. Without an efficient, accurate, and successful means of physically isolating the failure site, the rest of the analysis techniques cannot be implemented to their full potential. These studies support the emerging trend of failure analysis becoming a part of the manufacturing process, and not just an end-stage failure recovery plan. This is described as a "preemptive" methodology as opposed to a "reactive" methodology. Incorporating failure analysis into the production process can help find problems early and improve yield.

The equipment required to perform failure analysis on increasingly complex devices has become even more specialized and requires experience to both operate the machinery and interpret results for validity. In some cases, a Level 1 type of analysis can give quick results if the failure mechanism is obvious from optical inspection. A Level 2 analysis includes the additional tools necessary to find difficult, buried failure mechanisms which require extensive fault isolation and de-layering. A typical matrix of the failure analysis levels, their attributes, methods, and equipment needed for current and emerging analysis needs are summarized in Table 1-2.

Scanning electron and scanning probe microscopes are currently used for much of the high resolution, high magnification analysis. The Field Emission type of scanning electron microscopes (FESEM) have become the most popular due to their low maintenance and high resolution at low electron beam acceleration energies. It provides a very high magnification (up to 200,000x) with minimal interaction with the device. Gold deposition (conductive) coating is usually not required due to the lack of electron charging at low beam energies. De-capsulation (removal of the package to expose the die surface) and de-processing methods have generally adapted to the latest integrated circuit manufacturing techniques and are dependent on information from the fabrication houses to provide the best method and recipe for material removal. Traditional electrical probing equipment is reaching its physical design limits due to the extremely small line widths now used in multi-layer integrated circuits. To counter this, there are SEM probing systems being developed that have small probe tips and high magnification requirements such that they are able to make contact with sub-micron circuit features. Design for test (DFT) strategies are becoming integral to the initial design process to allow for both boundary scan, external continuity testing of high pin count components, and access to internal probe points for checking the electrical functionality of layered device elements that are not accessible from the top surface. Fault isolation techniques, like bit-fail maps and logic diagnostics, are critical in reducing the time required for electrical isolation.

As devices become smaller and approach nano-scale, contamination also poses a bigger threat to electrical functionality. As much as 60% of the defects in pilot line runs of new fabrication processes are attributed to "contamination", which is usually sub-micron particles that affect circuit patterning, and eventually electrical operation. Physical fault isolation methods such as liquid crystal, photon emission, and OBIRCH / LIVA (scanning laser probe excitation techniques) are integral to integrated circuit failure analysis that involves the location of very small current emission fault sites. New metalization processes, such as copper metalization, also require real-time analysis of defects throughout the many layers that they typically encompass.

The many new packaging methods employed today also impact the ability and success of component failure analysis. The chip density, size and heat issues encountered in CSP (Chip Scale Packaging), BGA (Ball Grid Array), SIP (System In Package), COB (Chip On Board), MCM (Multi-Chip Module) and Flip Chip technologies make it difficult to inspect and isolate top and/ or bottom die defects. Die back side thinning can be used in conjunction with Infra-Red microscopy to look through the back of the die in many cases, but this can still be difficult in a thick, multi-layer die with buried defects. The sensitivity of many of the surface excitation and fault isolation techniques utilized in finding buried defects is a continuing challenge with these new packaging methods.

Another important change that needs to take place in the coming years is a transition from destructive failure analysis techniques to non-destructive capabilities. One technique currently becoming popular is the use of X-rays in tomography (XRT). XRT uses the material dependent contrast of X-ray microscopy with precision sample rotation to look at "slices" of a material, and then software to reconstruct the tomographic three-dimensional image. It is possible to search for defects with resolution below 100nm. This would allow non-destructive localization of buried defects, and enable precise de-processing for later imaging with FIB (Focused Ion Beam), SEM, or TEM (Transmission Electron Microscopy). Figure 3-1 shows the various analysis techniques used in failure analysis and the typical resolution limits and overlap of each.

In summary, the future success of failure analysis on integrated circuit components relies on the latest advancements in fault isolation and high magnification inspection. With die and package features continuing to shrink, and the layers of integrated circuits increasing in both number and complexity, experience and innovation with the latest equipment available will be necessary to find failure mechanisms and root causes of failures. In the next decade, nano-scale devices will bring new failure mechanisms in the atomic scale range, and require advanced equipment that can resolve defects which are well beyond our current capability.

References
1.) International Technology Roadmap for Semiconductors 2001 Edition (http://public.itrs.net)

2.) "Choosing the Right Analytical Technique for Failure Analysis", Tabrez, Shams, Electronic Device Failure Analysis, Vol. 4 Issue 2, 2002, pp. 18-21.