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| A publication of the National Electronics Manufacturing Center of Excellence | January /February 2003 |
Detailed Description:
Recommendations Routing: One of the biggest concerns regarding routing is that even though the leads are smaller, they still have to carry the same amount of current. Since the amount of current a trace can carry is directly proportional to the cross-sectional area of the trace, the designer has two choices as to how to increase it. One is to increase the copper weight, which increases the cross-sectional area. However, increasing the height of the copper increases the minimum trace width that manufacturers can etch. Leaving the copper weight the same, means that the trace width must increase in order to maintain the current carrying capability of the trace. However, the traces of SMT boards are often much wider than the leads that they are connected to, which would cause shorting. The industry’s accepted method of dealing with this problem is to leave the trace width the same size as the PTH version and "neck down" the trace as it enters the lead. Another point of concern is fanout. PTH technology permits the pins of the component to pass through all layers of the board, while SMT devices only connect to the placement layer. Since the board in question was two-layered, the top side was used for component placement and routing traces, while the bottom side was used as a ground plane. That means that the ground connections of the components required using a via to the ground plane. Adding these vias caused congestion. The best way to avoid this is to space components away from each other, particularly near ground leads, thus allowing for more routing space. A final point on vias is that the more you introduce, the more you disturb the ground plane. Since the customer’s board had all of the board-level power and signal pins located at one side, the majority of the ground current flowed in a horizontal direction. The few traces required on the bottom side of the board were also oriented horizontally so that the ground currents could flow around the traces with minimal impact. Testability: The best method of testing a design is under actual operation. Since the board in question has all of the components on the top side and only a ground plane on the bottom, a bed of nails type circuit tester is an ideal choice. However, since the traces are almost all on the top side, a via must be added to each electrical net that does not already have one so that the tester can probe that particular net from the bottom side to determine voltage, current, and impedance. Manufacturability: A significant cost of board manufacturing is the hole count. The customer’s board contained a large number of different sized holes. The EMPF worked with the customer to reduce the number of hole sizes. Another point to consider regarding manufacturability is panelization. A panel can be assembled and tested quickly. It is critical to keep components, traces, planes, etc. away from the outer edges to avoided damage during the routing cut. Conclusion |
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