Customer Issue: The customer wanted to evaluate a proposed supplier’s capabilities to manufacture printed circuit boards (PCBs) that meet or exceed IPC specifications and their own internal PCB specifications that were based on the results of seven standard IPC tests.

The customer asked the EMPF Helpline staff to compare the product quality of their current PCB supplier to that of the proposed supplier. They wanted to obtain quantitative data for statistical qualification and tracking. The information would also be applied towards an evaluation of the effect their manufacturing process has on PCBs. The test used to ascertain this information was the dielectric withstanding voltage test.

Test Plans and Technique
The dielectric withstanding voltage tests were performed in accordance with IPC TM-650-2.5.7. The initial testing was performed at 500Vdc (spacing greater than 80um) for 30 seconds in accordance with IPC 6012A. Testing was continued at 50V intervals until failure, or until the limits of the test equipment were reached. The voltage was applied between conductor patterns of the individual layers and an electrically isolated pattern of the adjacent layers. Testing was performed on a total of 12 samples using the test set up shown below in Figure 2-1.

Purpose
The dielectric withstanding voltage test (also called high potential, over potential, voltage breakdown or dielectric strength test) applies a voltage higher than the test subject’s rated voltage for a specific duration between electrically isolated circuits and portions of a PCB, or between its isolated circuits, portions, and ground. The test is used to determine if the design (including materials and geometries) is adequate so that the PCB can operate safely at its rated voltage and be able to withstand transient over-voltage conditions caused by surges, faults, or other phenomena.

Background
Dielectric breakdown is a phenomena that typically must be avoided in circuit design to prevent failures leading to the replacement of the module and possibly further damage to adjacent circuits. However, some transient protection devices use dielectric breakdown as the method of protection.

Dielectric breakdown, in most laminates, typically results in localized oxidation and the destruction of the material’s electrical characteristics. The breakdown can either occur in the laminate itself, or as a result of “surface flashover”, where the material immediately adjacent to the laminate (i.e. air, oil, water, surface contaminates) suffers a breakdown. According to manufacturers’ data sheets, laminates commonly used in printed circuit boards have a dielectric breakdown voltage of at least 1000 V/mm of thickness. Thus, to withstand a 3KV transient surge, the laminate must be at least 3mm thick. With surface flashover, the root cause must be eliminated within the operational environment. If the circuit is exposed to surface contaminates, moisture, or variations in pressure, a conformal coating (with its own dielectric breakdown) should be considered.

Some transient suppression devices and circuits use dielectric breakdown as a shunt to shift energy away from the rest of the circuit. A transient suppression device is either a sealed device with a self healing dielectric (i.e. gas, oil) that will break down at a specific voltage, or it is an integral part of the PCB design that utilizes air as a dielectric. Gaps are cut in the PCB between circuits at a width that will provide creepage clearance and isolation during normal operation, but would cause a dielectric break down in the air between the circuits in a fault mode. The dielectric breakdown of air is defined by Paschen’s Law (V = f{pd}) or the Paschen curve. The curve is usually written as a graph of breakdown voltage (V) vs. the product of gas density (sometimes referred as pressure (p)) and gap size (d). For the designer, it should be noted that while the curve is defined by the function of the gas density and gap size, many other factors such as radiation, dust, surface irregularities, and humidity have an effect on the breakdown of a gap.

Results
The PCBs not only passed the criteria required by the IPC standard, but also the 1000V limitation of the test apparatus. The images in Figure 2-2 show the visual inspection results after the tests, and are representative of all PCBs tested. The image to the left is the top side of one of the PCBs to which wires were soldered. These wires allowed the high voltage testing to be performed at the location shown in the center image. The right image is the bottom side of the PCB. None of the boards that were tested showed physical damage from the application of high voltage.

Conclusion
No clear advantage in PCB quality between the two suppliers was obtained from dielectric withstanding voltage testing. However, some clear conclusions were deducted from the testing.

• The PWBs from each manufacturer exhibit similar dielectric characteristics.
• The current PWB fabrication quality exceeds the limitations of the specifications and test equipment.
• Although 500V was specified in the IPC test method, the boards showed no sign of failure when driven to 1000V.
• The current IPC dielectric withstanding voltage test is not an effective test for comparing the product quality of substrate manufacturers. The withstanding voltage test is commonly used as a quality control tool. When PWB quality is high, this test cannot efficiently compare the performance of one substrate manufacturer’s PCBs with that of another.

Future plans for test development include increasing test equipment capabilities to exceed 1500V. In addition, material analysis following testing may reveal micro-indicators that can be used to quantify board quality.