Customer Issue: The customer requested level 1 failure analysis of five power metal-oxide-semiconductor (MOS) transistor-integrated circuits. The customer also submitted one device of the same type as a known "good" reference.

Five devices were received from the customer with the manufacturer’s part number and lot number identifications. Level 1 failure analysis included visual inspection, X-ray, electrical testing, decapsulation, optical inspection, and scanning electron microscopy (SEM).

Results:
External Inspection:
Device #1 was the known "good" reference. The incoming condition of devices #2 and #3 was recorded, and they showed no major mechanical damage other than small mold compound chip-outs at one edge. Devices #4, #5, and #6 were also examined and photographed for severe electrical over-stress (EOS), thermal run-away damage, and device markings. Figure 4-1 shows device #4, which has a severe mold compound crack.

X-ray:
The internal lead-frame was observed with a live X-ray system with rotational capability. No anomalies were found with the X-Ray, although it was noticed (optically) that there were leads missing.

Electrical Test:
All devices were analyzed during the test using the datasheet supplied by the customer. Curve tracer analyses of the I-V characteristics revealed a low diode-type breakdown in device #2 and #3 between the drain and source, causing them to fail IDSS (as compared to the good unit). Short circuits between the gate, source, and drain were seen on each of the three remaining units.

Decapsulation:
In following ACI procedure AP0600-1, the plastic mold compound encapsulant was selectively removed on all of the failed devices to expose the active dies. The units were heated to approximately 200oC and were subjected to fuming sulfuric acid until the bond wires and dies were exposed. The components were then cleaned in a methyl alcohol bath.

Optical Inspection and Scanning Electron Microscopy:
The exposed lead-frames, bond wires, and die surfaces were inspected using a stereo microscope with digital image capture. A SEM was also used to examine the units in accordance with ACI lab procedure AP0280-1. Device #3 did not show any evidence of lead or package separation, other mechanical stress, or over-heating. Device #2 had a residual mold compound resulting from over-heating in the source metallization. Device #4 showed EOS with thermal run-away at the source bond pad, around the gate periphery, and around the gate pad. Figure 4-2 shows the photo of device #4 with EOS thermal run-away at the source (S) and gate (G) peripheries. Device #5 and #6 both showed massive EOS with vaporized source leads, and had EOS with thermal run-away damage covering much of the dies around their source and gate bond pads.

Conclusion:
Devices #2 and #3 showed evidence of EOS due to very high drain-source junction leakage during electrical testing, with a possible indication of overheating. Devices #4, #5, and #6 all showed failure due to massive EOS and thermal run-away caused by internal electrical shorts.

Recommendation:
The varying degrees of EOS seen between devices #2, #3, #4, #5, and #6 reveal that the devices, with respect to the drain current, are being stressed in an incremental fashion, and may not immediately fail in all cases. The mechanical integrity of the devices that were not severely damaged is normal, even after possible rework and removal. Screening of these devices to identify the pertinent characteristics that will allow some devices to withstand the circuit application may be possible. The best solution is obviously to re-design the circuit to be within the device specifications, or to replace the device with one that can withstand higher drain currents. Proper heat sink dissipation is also important to prevent additional over-loading.