Within the electronics industry, different measures have been taken to improve the ruggedization of integrated circuits (ICs). One measure has been the use of epoxy to under-fill the gap between the RF chip and the polymer substrate for improvements in physical reinforcement and the reliability of solder joints. This also reduces the coefficient of thermal expansion (CTE) mismatch. Another measure has been the addition of a coating to eliminate moisture and increase the life expectancy of components. However, in doing so, these measures may cause potential RF performance degradation. This article will address how to use RF modeling tools to predict performance degradation of chips or assemblies due to the addition of under-fillings and coatings during the manufacturing process.

Wire Bond Interconnection
The main parasitic characteristic of a wire bond is inductance. As the span of the bond increases, so does inductance. Second order geometry parameters are loop height and die height. The encapsulation material influences the capacitance of wire to ground. The coupling between two or more wire bonds must be considered as well. The parameter loop span, distance between loops, and the encapsulation material used are the main influences of RF characteristics. RF modeling with single inductance and an asymmetrical T-model accurately describes the Electro-magnetic (EM) simulation of wire bonds up to about 6GHz. For modeling up to 10GHz, a symmetrical T-model is necessary. Typical inductance values are in the range of 0.5nH. The dominant coupling effect is inductive coupling. Additional coupling results in higher model accuracy for higher frequencies.

Flip Chip (FC) Interconnection
The height of a flip chip’s interconnection influences its RF characteristics. An increase in the bump height of a flip chip (FC) increases the reflection coefficient of interconnection. Also, an increase in pitch will decrease coupling. The influence of under-fill material on coupling is frequency dependent, but without under-fill and a solder mask material, minimal coupling will be detected (7% for 30GHz). A solder mask with a dielectric constant above 1 (er=3.2) will cause an increase in coupling (up to 8%). Having an underfill material between the FC and the substrate leads to an increase of the coupling coefficient to approximately 40%. The capacitive coupling path will be influenced by a higher dielectric constant (er=3). An electrical model of FC interconnection consists of resistance, the inductance of the bumps, and the capacitance to ground (a pad parasitic). Due to pad geometry and bump size, the pad’s capacitance is the dominant value in a FC model. Additionally, the changing of a substrate or chip technology (material) does not impact the R/L model of a bump. The capacitance values will change however. Coupling between bumps can be modeled with mutual inductance and coupling capacitance.

RF Modeling of chips and Assemblies
A circuit simulator (CS) treats a component as a network of lumped elements in a time or frequency domain. The simulation of an entire circuit can be done quickly, but may have difficulties in handling circuits with strong coupling and radiation. A full-wave electromagnetic simulator (EMS), which is accurate, but computationally demanding, simulates the EM wave propagation in the circuit for different geometries either in a frequency or time domain. A CS uses the information obtained from an EMS, and connects hundreds of them to get the solution for the entire circuit. An EMS can handle coupling and radiation problems easily, whereas a CS will have difficulty.

Electromagnetic Field Calculation
Figure 5-1 shows a package geometry and the result of a 3D EM simulation. The electrical field magnitude and current density are visualized, as well as the RF characteristics and critical parts of the IC package. Based on the assumption that the package's signal transmission will take place in the fundamental propagation mode, compact element values can be determined. For the package with N pins, an NxN matrix can be calculated for capacitance (C), inductance (L), and resistance (R). The diagonally illustrated matrix values represent the individual values of each pin. The non-diagonal elements represent the coupling between corresponding pins. Typical C values of a TSOP (IC package type) structure are between 1pF and 1.8pF. Individual L values are in the range of 57nH. The coupling values decrease with a decrease in the number of pins. The matrix elements (L, C and R) are connected to form a compact model. This model is valid for frequencies up to approximately 5GHz. Circuit simulation signal behavior results are in the time domain. Also, delay, losses, and the coupling of lead frame structures can be investigated.

Conclusion
The RF characteristics of physically parameterized structures were computed using a 3D full wave EMS. The EM simulation results were very easily modeled as equivalent circuits using frequency independent R, L, and C elements. The influence of geometrical parameters and their relevance to the signal behavior of interconnections is inherent in the EM modeling. The modeling flow for chip-to-substrate interconnections is applicable for all packages. The modeling flow can separate RF effects caused by interconnections and the RF performance of pads. The information pertaining to the chosen substrate material and chip technology can be included in pad models.