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The trend in the worldwide RF electronics industry toward plastic packages and assemblies provides lighter weight and lower cost assemblies compared to the traditional hermetic metal or ceramic module packages. Because commercial applications encompass 98% of the RF electronics market, this RWOH movement has primarily affected the commercial sector, while the remaining 2% of the market composed of the military sector has yet to benefit.

This commercial trend utilizes the concept of “Near Hermeticity.” This concept entails the use of high performance organic materials to provide the required amount of hermeticity for the particular application, as measured by the Highly Accelerated Stress Test (HAST). Hermeticity has a range of values as evidenced by the graph in Figure 1-2, which shows a progression of hermeticity (or moisture immunity) from the less robust simple plastic packages, up to the high performance of a true hermetic Dual In-line Package (DIP) response to HAST testing.

In order to take advantage of this trend, Dow Corning has commercially introduced their Chip Seal® die coating on the semiconductor wafer level (before cutting into individual chips). HAST performance of packages using this commercially available multilayer coating is shown in Figure 1-3. The ChipSeal process involved the plasma enhanced chemical vapor deposition (PECVD) of silicon carbide coatings onto silicon wafers. These coatings, without any further organic coatings of the chips in individual chip form, significantly improve the ability of the silicon chips to withstand HAST testing. The hermetic Dual Inline Package (DIP) shown in Figure 1-3 performed the best; however, the standard hermetic DIP would cost and weigh significantly more than the ChipSeal® coated chip in a plastic, non-hermetic (but light and inexpensive) package. In addition, the gap between the performance results of the two types of packages was not that wide.

One of the dimensions that Raytheon will add to the current project will be the definition of hermeticity requirements that the coated die must meet. The current project also maintains the option of applying coating a second time, over the chip coating, after the chip has been singulated out of the coated wafer. An organic assembly coating material, such as a conformal coat, would add a second layer to the already relatively effective wafer level silicon carbide PECVD coating.

The adhesion of the wafer level silicon carbide coating to the gallium arsenide (GaAs) material of the RF chip is one of the challenges of the current EMPF project, as the initial Dow Corning work used aluminum metallized silicon digital chips rather than gold metallized GaAs RF chips. RF die are usually made from gallium arsenide rather than silicon because of its RF properties. This project will determine methods of applying such a multi-stage, hermetic coating to RF die, and will include the standard hermetic enclosure with non-coated chips as the “control,” to provide a baseline for comparison.

The coating of the RF chips in the wafer form, if “hermetic enough” for the application, represents significant potential cost and weight advantages. By “hermetic enough,” it is meant that the coatings impart sufficient immunity for the RF chips against the deleterious effects of moisture and/or ionic impurities, close to that of a traditional hermetic enclosure. The traditional hermetic enclosure would be one in which the helium leak rate was low enough to allow definition of the enclosure as “truly hermetic.”

In order to further reduce the cost of RF electronic modules (e.g., T/R modules for phased array radars) and provide the application of a hermetic coating to a multi-chip assembly, the commercial industry and the EMPF are actively pursuing the introduction of all-organic, near-hermetic solutions which, in addition to the ChipSeal® wafer level coating, can be applied at the module level to all types of chips being used, including both silicon (digital) and gallium arsenide (RF) chips.

The current EMPF project will test and validate various chip and assembly level coatings for their hermetic qualities and provide results in February 2006. The results will reveal coating techniques which can be implemented by both commercial and military electronics manufacturing sectors.